SoC Design Verification Engineer, Silicon

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or in a related field, or equivalent practical experience.
• 8 years of experience with verification methodologies and languages such as UVM and SystemVerilog.
• Experience in developing and maintaining Design Verification (DV) testbenches, test cases, and test environments.

Preferred qualifications:

• Master's degree in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience in different verification techniques and methodologies including formal, GLS, UPF based Power simulations, UVM and C based testing, etc. to achieve bug-free Silicon in complex SoCs.
• Experience with post silicon pattern generation and preparation.
• Experience with post silicon debug.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

• Plan the verification of complex digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.
• Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM).
• Identify and write all types of coverage measures for stimulus and corner-cases.
• Debug tests with design engineers to deliver functionally correct design blocks.
• Close coverage measures to identify verification holes and to show progress towards tape-out. Participate with architecture, design teams, Sival to define the overall verification strategy of System on a Chips (SoC).