ASIC Design For Testability Engineer, Silicon

Minimum qualifications:

• Bachelor's degree in Computer Science, Electronics or Electrical Engineering, or equivalent practical experience.
• 5 years of experience in ASIC design for test including complete silicon life cycle through DFT pattern bring-up on ATE and manufacturing.
• Experience with ATPG, Low Power designs, BIST, JTAG, IJTAG tools and flow.
• Experience with DFT EDA tools (e.g., Tessent).

Preferred qualifications:

• Experience with DFT for subsystems with multiple physical partitions.
• Experience with IJTAG ICL, PDL terminology, ICL extraction, ICL modeling with Siemens Tessent tool.
• Experience with Spyglass-DFT, and DFT Scan constraints, and evaluating STA paths.
• Experience in developing automated workflows using Python and Tcl.
• Experience in collaborating with Design, PD, and STA teams.

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

• Work with a team of DFT engineers, RTL and Physical Designer Engineers.
• Work on Subsystem level DFT SCAN, MBIST Architecture with multiple voltage, power domains. 
• Write scripts to automate the DFT flow.
• Develop tests that can be used for Production in the ATE flow.