Senior ASIC Design Engineering, Silicon

Minimum qualifications:

• Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience.
• 3 years of experience with Register-Transfer Level (RTL) design using Verilog/System Verilog and microarchitecture.
• Experience in handling low power schemes, power roll up and power estimations.
• Experience in Register-Transfer Level (RTL) quality sign-off flows (e.g., CDC, RDC, Lint, Power Intent or LEC).
• Experience with Perl or Python.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science.
• Experience with methodologies for low power estimation, timing closure, and synthesis.
• Experience with computer architecture.

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

• Define microarchitecture details such as interface protocol, block diagram, data flow, pipelines, etc.
• Perform Register-Transfer Level (RTL) development (SystemVerilog), RTL integration (Perl), debug functional/performance simulations.
• Perform RTL quality checks including Lint, CDC, RDC, Synthesis, Unified Power Format (UPF) checks.