Lead CPU RTL Front End Design Engineer, Subsystem

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• 10 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
  
• Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques.
  
• Experience with RTL language (System Verilog) and related design processes (e.g., Lint, UPF).

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience leading front-end design for modern processor components or AI accelerators.
• Experience with ARM Instruction Set Architecture.
• Experience with SOC design, architect, and integration.

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

The US base salary range for this full-time position is $221,000-$314,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

• Participate in developing CPU subsystem. Develop CPU subsystem front-end designs, emphasizing on microarchitecture and RTL design for the next generation CPU.
• Communicate the pros and cons of microarchitecture enhancements. Deliver designs, meeting PPA goals with production quality.
• Work with the Verification team to ensure production of quality designs, and the physical design and power teams to meet frequency, power, and area goals.
• Become familiar with modern techniques, interpret the techniques into design constructs and languages in order to provide guidance to and participate in the performance evaluation effort.
• Propose performance enhancing microarchitecture features, and work with Software, Architect, and Performance teams for trade-off studies.