Minimum qualifications:
- Bachelor's degree in Electrical Engineering or Computer Science or equivalent practical experience.
- 2 years of experience in Design Engineering.
- Experience with SoCs and Chip Flow Design.
Preferred qualifications:
- Master's degree in Electrical Engineering or Computer Science.
- Experience in micro-architecture and coding in one or more of these areas: memory compression, interconnects, coherence, cache.
- Good understanding of Verilog or System verilog language.
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
- Work on both the IP design and integration activities including: plan tasks, support, hold code and design reviews, contribute on sub-system/chip-level integration.
- Interact closely with the architecture team and develop implementation strategies to meet quality, schedule, and power performance area for IPs.
- Interact closely with the subsystem team and plan SOC milestones, and plan quality checks as part of SOC milestones (e.g., IPXACT, CSR, Lint, CDC, SDC, UPF, etc.).
- Work closely with cross-functional teams of verification, design for test, physical design, emulation, and software to make design decisions and represent project status throughout the development process.
