Design Verification Engineer, ASIC

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Science or equivalent practical experience.
• 5 years of experience in coding, developing test methodologies, writing test plans, creating test cases, and debugging.
• Experience verifying digital logic at RTL level either using SystemVerilog, C, C++.

Preferred qualifications:

• Master's degree in Electrical Engineering or Computer Science or equivalent practical experience.
• Experience with Interconnect Protocols such as AHB, AXI, ACE, CHI, CCIX, CXL.
• Experience with performance verification of SOC, Pre-Silicon analysis and post-Silicon correlation.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

• Plan and execute the verification of the next generation configurable Infrastructure Intellectual Property (IPs), interconnects and memory subsystems.
• Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM).
• Develop cross language tools and verification methodologies.
• Identify and write all types of coverage measures for stimulus and corner-cases.
• Debug tests with design engineers to deliver functionally correct blocks and subsystems