Formal Verification Engineer Subsytem, Silicon

Minimum qualifications:

• Bachelor's degree in Mechanical Engineering, Electrical Engineering, Industrial Engineering or equivalent practical experience.
• Experience in formal verification applications (e.g., sequential equivalence checking, and connectivity checking) and data-path verification.
• Experience with formal sign-offs of industry ASIC designs.
• Experience with scripting languages (e.g., Python/Perl, and TCL).
• Experience with formal methodologies and abstraction techniques.

Preferred qualifications:

• Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science, or equivalent practical experience.
• 5 years of experience with SystemVerilog and SystemVerilog Assertion.
• Experience with formal verification, Formal Property Verification, different complexity reduction techniques and different abstractions.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

• Plan the formal verification strategy, create the properties and constraints for complex digital design blocks.
• Utilize formal property verification tools combined with formal verification closure techniques to verify properties.
• Contribute improvements to methodologies to enhance formal verification results.