CPU Timing Closure Lead, Silicon

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• 8 years of experience with physical design flow such as constraints, synthesis, floor planning, place and route, clock tree synthesis (CTS), or physical verification.
  
• Experience in high speed design timing convergence and in Static Timing Analysis tools like Primetime or Tempus.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  
• Experience and understanding in engineering across timing analysis and design implementation.
• Experience in the delivery of high performance silicon in latest technology process nodes.
• Knowledge of semiconductor device physics and transistor characteristics.
• Strong scripting and data mining skills, extraction of design parameters, metrics and analyzing data trends.

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

The US base salary range for this full-time position is $177,000-$266,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

• Drive the sign-off timing convergence for high performance designs. 
  
• Setting up the timing constraints, defining the overall Static Timing Analysis (STA) methodology, STA infrastructure and sign-off convergence flows
  
• Collaborate with the RTL design teams on microarchitecture critical items for timing and power convergence.
  
• Drive or develop physical design timing convergence tools and flows for advanced CPU designs to achieve outstanding Power Performance Area (PPA).