CPU Frontend Design Engineer, Google Cloud, University Graduate -

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
• Experience in full VLSI design cycle.
• Experience in RTL implementation of low power designs.
  
• Experience in VLSI development with Verilog, SystemVerilog, System Verilog Assertions (SVA), or VHDL, and with design verification, synthesis, timing/power analysis, and DFT.
  

Preferred qualifications:

• Experience in four or more SoC cycles.
• Knowledge of modern high-performance CPU architecture and micro-architecture.
  

As a CPU Frontend Design Engineer, you will take part in central processing unit (CPU) development, a complex and critical blocks of Google’s sever System on a Chip (SoC). You will be responsible for microarchitecture and RTL design and implementation of core technology as part of Google’s data center SoC products. You'll collaborate closely with architecture, verification, and physical design engineers, creating micro-architectural definitions with RTL coding and running block level simulations.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

• Define architecture and micro-architecture features, write specifications, and understand implementation tradeoffs (e.g., performance, power, frequency, etc.).
• Define the CPU block level design document (e.g., interface protocol, block diagrams, transaction level flow, control registers, pipelines, etc.).
• Perform RTL development process (e.g., coding and debug in Verilog, SystemVerilog, or VHDL), function/performance simulation debug, and Lint/CDC/FeV/PowerIntent checks.
• Contribute to the SoC level integration, and participate in synthesis, timing/power closure, and silicon bring-up.
• Participate in test plan and coverage analysis of the block and SoC-level verification.