Tensor SOC Performance DV Engineer

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 3 years of experience with verification methodologies and languages such as UVM and SystemVerilog.
• Experience verifying digital logic at the Register Transfer Level (RTL) using SystemVerilog at Subsystem or Full chip level.
• Experience in performance and latency architecture for an Anycast Redirector Maglev (ARM) based SOC.
• Experience in mobile SOC performance model development, performance analysis, and workload characterization.
• Experience performance measurement and debugging in an emulation environment.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience in low-power design verification.
• Experience in microarchitecture innovation.
• Knowledge of CPU, GPU benchmark characterization.
• Knowledge in system software components, such as Linux, drivers, and runtime.
• Knowledge of performance analysis tools.

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

• Develop simulators and architectural models of Google's Tensor System on a Chip (SOC).
• Collaborate with system architects, SoC and CPU/GPU/TPU architects/designers, and software and application experts to understand current and future requirements.
• Participate in architectural and design evaluation of Tensor SOC features studies.
• Perform pre-silicon performance simulation and correlate with pre and post-silicon measurements.
• Communicate analysis results qualitatively and quantitatively.