Infrastructure Tools and Methodology Lead

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 10 years of experience with industry-standard tools, languages and methodologies relevant to the development of silicon-based ICs and chips.
• 6 years of experience in people management, developing employees.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience planning and deploying new tools and flows to users.
• Knowledge of chip design process, either verification, design or implementation.
• Ability to present and explain novel methods to users.

As a Hardware Engineer, you will design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the influence to design the machinery that goes into our data centers affecting millions of Google users.

As a Technical Lead within Google's hardware team, you will help deliver products that have an impact on the Technical Infrastructure that powers Google. You will provide leadership to a group of hardware engineers in an innovative and fluid environment with a focus on infrastructure for chip design. You will also lead complex technical projects from the concept/planning stage through execution and closure. In this role, you will help your team deliver designs that work first time in a number of different application areas. Leveraging your technical and leadership expertise, you lead chip design process improvement projects in multiple areas of expertise.

• Lead chip methodology engineers to provide support for chip teams, and also manage and mitigate support issues for tool flows.
• Partner with chip project teams to influence and standardize methodology across functional areas (Design, DV, PD).
• Perform or guide technical evaluations of tools for possible deployment.
• Collaborate with teams across Google to identify and create strategic opportunities for improved chip design across Google.
• Participate in design reviews and track issue resolution and engage in technical and schedule trade-off discussions.