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Google

Formal Verification Engineer, Platform IP

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🌍Bengaluru, Karnataka, India
11h ago
πŸ‘€ 1 views
πŸ“₯ 0 clicks

Job Description

Minimum qualifications:

  • Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
  • 3 years of experience with Formal Verification (e.g., sequential equivalence checking, Security Path verification, connectivity, low power and Formal property verification).
  • Experience with programming languages (e.g., Python/Perl and TCL).

Preferred qualifications:

  • Master's degree or PhD in Electrical Engineering, Computer Science, or a related field.
  • Experience with regression setup and management.
  • Experience with formal sign-offs of industry Application-specific integrated circuit (ASIC) designs.
  • Knowledge of formal verification applications such as sequential equivalence checking, and connectivity checking and data-path verification.
  • Knowledge of formal methodology and formal abstraction techniques.
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
  • Plan the formal verification strategy, create the properties and constraints for digital design blocks.
  • Use different formal verification applications to resolve multiple tests like clock-gating verification, low power, connectivity and security path verification.
  • Utilize formal property verification tools combined with formal verification closure techniques to verify properties.
  • Contribute improvements to methodologies and scripting to enhance formal verification results.
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