Physical Design Engineer, Physical Verification and Convergence

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 3 years of experience in physical design, verification, and various methodologies.
• Experience in Python, Tcl, or Perl scripting.

Preferred qualifications:

• Master's degree in Computer Engineering, Electrical Engineering, Computer Science, a related field, or equivalent practical experience.
• 3 years of experience in ASIC physical design flows with emphasis on physical verification convergence and tapeout signoff.
• Experience in full chip physical verification signoff on tapeouts on advanced nodes.
• Experience in Padrings, Bumps, Redistribution Layer (RDL) and IP integration (memories, IO's and analog IPs).
• Experience in PnR tools like FusionCompiler or Innovus with regards to physical convergence.
• Knowledge of semiconductor device physics and transistor characteristics.

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

The US base salary range for this full-time position is $127,000-$187,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

• Own and perform physical verification steps including DRC, LVS, ERC, ANT, DFM at the block, subsystem and fullchip level.
• Contribute to process flow and methodology for full chip assembly and tapeout signoff.
• Work with floorplan and physical design engineers to drive physical verification convergence.
• Perform technical physical evaluations of vendors, process nodes and IP.
• Contribute to design methodologies and automation scripts for physical verification steps.