Senior ASIC DFT Engineer, Silicon

Minimum qualifications:

• Bachelor's degree in Electrical or Electronics Engineering or equivalent practical experience.
• 8 years of experience in DFT Methodologies.
• Experience with DFT Electronic Design Automation (EDA) tools like Tessent.
• Experience with Automatic Test Pattern Generation (ATPG), Low Power designs, Built-In Self Test (BIST), Joint Test Action Group (JTAG), Internal Joint Test Action Group (IJTAG) tools and flow.

Preferred qualifications:

• Experience architecting/developing DFT flows and methodologies.
• Experience in collaborating with Design, Physical Design (PD) and Static Timing Analysis (STA) teams.
• Excellent scripting skills in languages like Python and TCL.

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will work with a team of Design for Testing (DFT) engineers, working closely with Register-Transfer Level (RTL) and Physical Designer Engineers. Work on Subsystem level DFT SCAN, MBIST Architecture with multiple voltage and power domains.
Write basic scripts to automate the DFT flow. Develop tests that can be used for Production in the Automatic Test Equipment (ATE) flow.

Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology.

• Work with a team of DFT engineers, working with RTL and Physical Designer Engineers.
• Work on Subsystem level DFT SCAN, Memory Built-In Self Test (MBIST) Architecture with multiple voltage, power domains. 
• Write basic to scripts to automate the DFT flow.
• Develop tests that can be used for Production in the ATE flow.