ASIC Design Engineer, Silicon

Minimum qualifications:

• Bachelor’s degree in Electrical or Computer Engineering or equivalent practical experience.
• 6 years of experience with ARM-based System on a chip (SoCs), interconnects and Application-Specific Integrated Circuit (ASIC) methodology.
• 5 years of experience with Register-Transfer Level (RTL) design using Verilog/System Verilog and microarchitecture.
• Experience with a coding language like Python or Perl.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Science, or equivalent practical experience.
• 6 years of industry experience with Internet Protocol (IP) design.
• Experience with methodologies for Register-Transfer Level (RTL) quality checks (e.g., Lint, CDC, RDC).
• Experience with methodologies for low power estimation, timing closure, synthesis

In this role, you will design foundation and chassis Internet Protocols (IPs) (e.g., Network on Chip (NoC), Clock, Debug, IPC, Memory Management Unit (MMU) and other peripherals) for Pixel System on a chip (SoCs). You will collaborate with members of architecture, software, verification, power, timing, synthesis etc. to specify and deliver a quality Register-Transfer Level (RTL). You will solve technical problems with micro-architecture, low power design methodology and evaluate design options with performance, power and area in mind.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

• Participate in test planning and coverage analysis.
• Develop Register-Transfer Level (RTL) implementations that meet power, performance and area goals.
• Participate in synthesis, timing/power closure and Field Programmable Gate Array (FPGA) and silicon bring-up.
• Perform Verilog/SystemVerilog RTL coding, functional, performance simulation debug and Lint/CDC/FV/UPF checks.
• Create tools/scripts to automate tasks and track progress.