Silicon Design Verification Manager

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 10 years of industry experience in Design Verification.
• 4 years of experience in people and project management.
• Experience leading a team completing the full functional verification of variety of designs at IP and subsystem level.
• Experience constructing reusable verification components and environments using UVM, System Verilog or equivalent.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering or Computer Science, or a related field.
• Experience in one or more of the following: Operating Systems, Memory Management, Caches Hierarchies, Coherency, Memory Consistency Models, Memory Ordering, DDR/LPDDR, PCIe, or Packet Processors.
• Experience working with software teams to define hardware/software interfacing including control/status registers, security, and error handling.
  
• Experience with Formal verification techniques, System Verilog Assertions (SVA) and assertion-based verification.
  
• Experience building verification methodologies that span simulation, emulation and FPGA prototypes.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

• Lead and manage a team of design verification engineers performing tasks related to IP verification from start to closure.
• Plan complete verification of these IPs by fully understanding the design specification, their usage in the subsystem, SOC and interacting with architecture and design engineers to identify important verification scenarios.
• Provide technical leadership to design verification engineers to create and enhance constrained-random verification environments using System Verilog and UVM.
• Be responsible for delivering these completely verified IP by planning on deploying verification techniques like configurable test benches, constrained random, functional coverage, etc.
• Be the primary point of contact for all design verification related activities for these IPs.