SoC Performance Verification Engineer, Silicon

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 4 years of experience with Design Verification with 2 years in formal verification.
• Experience in verifying digital logic at RTL level using Systemverilog/UVM and FV Techniques.
• Experience with digital systems using standard IP components/interconnects (microprocessor cores, hierarchical memory subsystems).

Preferred qualifications:

• Master's degree in Electrical Engineering or Computer Science.
• Experience creating and using verification components and environments in a standard verification methodology such as UVM.
• Experience in Verilog, VHDL, SystemVerilog.

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

• Plan and execute the verification of the next generation configurable interconnect, memory management, power controller, and chips pervasive IP.
• Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools.
• Develop cross-language tools and scalable verification methodologies.
• Debug tests with design engineers to deliver functionally correct design blocks. Identify and write all types of coverage measures for stimulus and corner-cases.
• Close coverage measures to identify verification holes and to show progress towards tape-out.