Layout CAD Engineer, Silicon

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
• 5 years of experience in semiconductor layout flow development and automation.
• Experience in Scripting languages such as Python or TCL.

Preferred qualifications:

• Master's degree in Electrical Engineering, Computer Science or equivalent industry experience.
• Experience in using physical design tools such as place and route tools, and layout verification tools.
• Experience in developing memory compiler software.
  
• Knowledge of LEF collateral verification, Caliber tool Suite and standard-cell layout.
• Knowledge of layout integration challenges.

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

• Collaborate with layout engineers to identify critical checks that ensure correctness and robustness of standard-cells and memory arrays.
• Architect and drive the development of checkers to identify patterning and abutment issues in the design.
• Drive the development of a memory compiler. 
• Streamline existing workflows and create new ones based on project requirements.