Circuits Design Engineer, Clock Design, University Graduate, PhD, Machine Learning

Minimum qualifications:

• PhD degree in Electrical Engineering or equivalent practical experience.
• Experience in clock architecture and designing high speed clock distribution circuits.
• Experience in Spice simulations, clock verification, and signoff.

Preferred qualifications:

• Experience in ASIC physical design, physical design flows, and methodologies including synthesis, place and route, Static Timing Analysis (STA), formal verification, Change Data Capture (CDC), and power analysis.
• Experience in IP integration (e.g., Phase Lock Loops (PLLs), memories, and Analog IP) and analog routing.
• Experience in a scripting language (e.g., Python, Perl or TCL).
• Knowledge of Verilog/System Verilog.
• Familiarity with low power design techniques (e.g., multi Vth/power/voltage domain design, clock gating, power gating, Dynamic Voltage Frequency Scaling (DVFS)/AVS, etc.).

As a Circuits Design Engineer, Clock Design you will collaborate with the architecture, logic design DFT, physical design, and circuits/technology teams to overcome the slowing of Moore’s Law in advanced technology nodes and deliver cutting edge ASIC’s and SoC’s. You will drive block and full-chip level physical implementation of clock distribution and optimize related quality of results (i.e., power, timing, area). You will perform technical evaluations of EDA vendors, process nodes, and IPs and will provide recommendations. You will develop new and novel solutions and methodologies that co-optimize across the entire design space, then see these through from inception to maturity and tapeout.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

The US base salary range for this full-time position is $127,000-$187,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

• Perform full chip clock planning. Create timing constraints and own the physical implementation of clock macros.
• Perform Spice simulations and run sign-off checks for the full-chip clock.
• Work with logic designers to drive architectural feasibility studies, develop timing, power, and area design targets, and explore RTL/design tradeoffs for physical design closure.
• Perform technical evaluations of vendors, process nodes, and IPs and provide recommendations.
• Collaborate with teams across Google to develop ideas for high-impact clocking innovations for chip design projects.