TPU RTL Design Engineer, University Graduate, PhD, Machine Learning

Minimum qualifications:

• PhD degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• Academic, educational, internship, or project experience with RTL coding and Verilog/SystemVerilog.

Preferred qualifications:

• Experience with digital clock control circuits.
• Experience interacting with software, architecture, and other cross-functional teams.
• Experience with a scripting language (e.g., Python or Perl)
• Knowledge of processor design or accelerators.
• Knowledge of high-performance and low power design techniques.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

The US base salary range for this full-time position is $127,000-$187,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

• Work mostly independently to create and review clock control subsystem's design microarchitecture specifications.
• Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines.
• Work with architecture and power teams to evaluate features and their impact.
• Work with design validation (DV) teams to create test plans to verify, and debug design RTL.
• Work with physical design teams to ensure design meets physical requirements and timing closure.