Senior Software Engineer, ASIC TPU, Google Cloud Platform

Minimum qualifications:

• Bachelor's degree or equivalent practical experience.
• 5 years of experience with software development in one or more programming languages, and with data structures/algorithms.
• 5 years of experience in system software development with C or C++.
• 3 years of experience testing, maintaining, or launching software products, and 1 year of experience with software design and architecture.

Preferred qualifications:

• Master's degree or PhD in Computer Science, or a related technical field.
• Experience with High-Bandwidth Memory (HBM), Peripheral Component Interconnect Express (PCIe), and ARM.
• Experience in hardware/software co-design at the chip-level.
• Experience with security and confidential computing.
• Experience in embedded systems.
• Experience with Machine Learning.

In this role, you will develop C++ code that controls and monitors Google’s custom accelerators (ASICs) - including TPUs (for machine learning) and Video Coding Units (VCUs) for video encode/decode. You will also define the API that the rest of the software stack uses to build planet-scale deployments of the systems that use these ASICs. You will write code that handles interrupts, Direct Memory Access, and many other hardware-centric features. You have role in the initial debug and bring-up of new ASICs and are among the first teams to use the new chips.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

• Architect, design, and build firmware running on embedded microcontrollers with limited memory footprints on the accelerator Application-Specific Integrated Circuit (ASIC) such as power-on and reset of the ASICs, initializing low level hardware, power management, and security.
• Contribute to all layers of the data center software stack to deploy accelerator ASICs to production.
• Architect, design and develop tools to update and debug ASIC firmware. Enable chip bring-up and hardware debugging.
• Build functional or cycle level simulators that bit accurately and model the custom accelerator ASICs. Build tools and infrastructure to help ASIC design verification, tapeout, and bring-up. Develop embedded CPU simulators as part of the full system simulator.
• Co-design hardware/software interface, work with the Hardware Design and Development teams.