Senior CPU Physical Design Engineer, Silicon

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• 5 years of experience with physical design flow such as constraints, synthesis, floor planning, place and route, clock tree synthesis (CTS), or physical verification.
  
• Experience in one or more sign-off convergence areas.
• Experience in high-speed design, including implementation and Power Performance Area, leveraging industry-standard tools.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience in the delivery of high performance silicon in latest technology process nodes.
• Experience in extraction of design parameters, QoR metrics and analyzing data trends
• In-depth understanding of Static Timing Analysis including sign-off corner definitions.
• Strong scripting and data mining skills.
• Understanding of Electromigration and Voltage drop flows and design for high frequency designs to support reliability.

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

The US base salary range for this full-time position is $150,000-$223,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

• Work closely with Frontend and Architecture teams to drive architectural feasibility studies, identify power-performance-area tradeoffs for physical design closure.
  
• Drive block/IP physical design implementation and drive continuous Power & Performance improvements through synthesis and Place & route trials. Work in a tight loop with RTL designers to debug timing paths to drive best implementation choices.
  
• Develop physical design methodologies using industry standard EDA Tools and developing design customization for implementation.
  
• Work on sign off areas such as Static Timing Analysis & Electrical Checks.