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Apple

Mixed-Signal Model Validation Engineer

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Austin, Texas, United States

3d ago
πŸ‘€ 10 views
πŸ“₯ 0 clicked apply

Job Description

Description

Description
In this job you will be responsible for verifying mixed-signal behavioral models written in SystemVerilog. The verification process will involve creating self-checking testbenches to simulate models against the circuits they were derived from. It will also involve functional testing of the model against the specification and creating assertions to flag illegal operating conditions. You will additionally help setup and run various static flows like formal logical equivalence, linting, and timing checks. You will also contribute to the streamlining and automation of these flows across mixed-signal design teams.

Minimum Qualifications

Minimum Qualifications
  • Bachelor’s degree with minimum 3 years of relevant experience

Key Qualifications

Key Qualifications

Preferred Qualifications

Preferred Qualifications
  • Excellent knowledge of SystemVerilog and Assertions
  • Ability to read custom circuit schematics and understand functionality
  • Solid understanding of logic/SPICE simulations as well as SPICE/HDL co-simulations
  • Excellent knowledge of digital logic gates, clocking and state elements
  • Basics of passive and active circuit elements, voltage and current sources, and analog blocks like amplifiers ADCs/DACs/Comparators
  • Familiarity of writing scripts in PERL/Python is a strong plus
  • Familiarity with formal equivalence and Lint/CDC/RDC tools is a strong plus

Education & Experience

Education & Experience

Additional Requirements

Additional Requirements

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  • Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.

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