Power Management Validation Engineer, Silicon

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• 3 years of experience developing random stress tests, silicon validation frameworks, or related infrastructure.
• Experience in one or more areas in IP level power management, DVFS, SoC/CPU/memory power management.
• Experience programming in C/C++.
• Experience with ARM architecture.

Preferred qualifications:

• Experience executing tests on emulation platforms or FPGA.
• Experience with JTAG debuggers (e.g., Lauterbach).
• Experience with board level debug.
• Experience with complex system debug, embedded operating systems and bare metal programming.
• Knowledge of OS fundamentals and low power design and architecture techniques.
• Familiarity with PMIC and power modeling techniques.

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

• Plan, develop, and execute tests to validate IP, subsystem and system level power management.
• Manage power correlation and power management design validation on pre-silicon and post-silicon platforms
• Interface with Software, Architecture, Design, and Domain Validation teams to create and execute test plans.
• Support silicon debug and field failures.