Application-specific integrated circuit (ASIC) Design Verification Engineer

Minimum qualifications:

• Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience.
• 3 years of experience in Design Verification, verifying digital reasoning at Register-Transfer Level (RTL) level using C/C++, SystemVerilog or Universal Verification Methodology (UVM).
• Experience in verifying digital systems using standard Internet Protocol (IP) components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems).
• Experience in creating and using verification components and environments in standard verification methodology.
• Experience in coding languages and software development frameworks.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering or Computer Science, or equivalent practical experience.
• 5 years of experience with architecture in Caches Hierarchies, Coherency, Memory Consistency Models, DDR/LPDDR, PCIe, Packet Processors, Security, Clock and Power Controllers.
• Experience with Interconnect protocols (e.g., AHB, AXI, ACE, CHI, CCIX, CXL) with performance verification of System on a Chip (SOCs), pre-silicon analysis and post-Silicon correlation.
• Experience with building verification methodologies with simulation, emulation and Field Programmable Gate Array (FPGA) prototypes.

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

• Plan and execute the verification of the next generation configurable Infrastructure Internet protocols (IPs), interconnects and memory subsystems.
• Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM).
• Develop cross language tools and scalable verification methodologies.
• Identify and write all types of coverage measures for stimulus and corner-cases.
• Debug tests with design engineers to deliver functionally correct blocks and subsystems. Close coverage measures to identify verification holes and to show progress towards tape-out.