Silicon Design Lead, Network on Chip, Intellectual Property

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience with digital design in ASIC.
• 4 years of experience in people management.
• Experience with RTL design using Verilog/System Verilog and microarchitecture.
• Experience with ARM-based SoCs, interconnects, and ASIC methodology.

Preferred qualifications:

• Master’s degree in Electrical Engineering or Computer Engineering.
• Experience with methodologies for low power estimation, timing closure, and synthesis.
• Experience leading IP/SoC design team for low power SoCs.
• Ability to drive a multi-generational roadmap for IP/SoC development.

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology.

• Lead the team that delivers coherent fabric interconnect solutions.
• Define microarchitecture details such as interface protocol, block diagram, data flow, pipelines, etc.
• Oversee Register-Transfer Level (RTL) development, debug functional/performance simulations.
• Participate in synthesis, timing/power estimation and field-programmable gate array (FPGA)/silicon bring-up.
• Drive multi-generation roadmap for design updates and optimization.