This role will give you ownership of all aspects of design and development of large SOCs, SOC blocks and sub-systems. Handle internal/external IP integration and build sophisticated sub-systems Our engineers design the SOC top level with IPs, sub-systems, PHY-macros, IO/PAD-ring system bus and other infrastructure components for clocking, reset and power-management. We build the integration specs that you develop, run QC checks to ensure quality, create UPF, run synthesis and generate netlist, and close timing for the block. Work closely with Chip Architecture, Design Verification, Physical Design, DFT and power teams to achieve SOC tapeout goals on schedule. Develop and maintain methodology/flows/checks for your design. Work with multi-disciplinary groups to make sure designs are delivered on time and with the highest quality by incorporating accurate checks at every stage of the design process.