Senior Multimedia Design Verification Engineer, Silicon

Minimum qualifications:

• Bachelor's degree in Electrical Engineering or Computer Science, or related field, or equivalent practical experience.
• 10 years of industry experience in Design Verification.
• Experience leading a team completing the full functional verification and performance validation cycle of subsystems such as multimedia, communication, or processors, or at the SOC level.
• Experience constructing reusable verification components and environments using UVM.

Preferred qualifications:

• Experience with image processing or other multimedia IPs such as Display or Video Codec.
• Experience with System Verilog Assertions (SVA), assertion-based verification, and formal verification.
• Experience working with software teams to define hardware/software interfacing including control/status registers, security, and error handling.
  
• Experience working with RTL design and integration teams on methodologies that improve team productivity and velocity.
  
• Experience with Low Power Verification and power management flows.
• Experience with Zero Delay, SDF, and Power Aware GLS at block and SOC level.

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

• Plan the verification of multimedia Intellectual Properties (IPs) at Subsystem and full chip level by fully understanding the design specification and interacting with architecture and design engineers to identify important verification scenarios.
  
• Create and enhance constrained-random verification environments using System Verilog and Universal Verification Methodology (UVM).
  
• Identify and write all types of coverage measures for stimulus and corner-cases.
  
• Debug tests with design engineers to deliver functionally correct design blocks.
  
• Close coverage measures to identify verification holes and to show progress towards tape-out.