Senior Hardware Engineer, Design and Architecture - Mountain View

At Google DeepMind, we value diversity of experience, knowledge, backgrounds and perspectives and harness these qualities to create extraordinary impact. We are committed to equal employment opportunity regardless of sex, race, religion or belief, ethnic or national origin, disability, age, citizenship, marital, domestic or civil partnership status, sexual orientation, gender identity, pregnancy, or related condition (including breastfeeding) or any other basis as protected by applicable law. If you have a disability or additional need that requires accommodation, please do not hesitate to let us know.

Snapshot:

At Google DeepMind, we've built a unique culture and work environment where long-term ambitious research can flourish. We are seeking a highly motivated Hardware Engineer to join our team and contribute to development of groundbreaking silicon for machine learning acceleration.

About us:

Artificial Intelligence could be one of humanity’s most useful inventions. At Google DeepMind, we’re a team of scientists, engineers, machine learning experts and more, working together to advance the state of the art in artificial intelligence. We use our technologies for widespread public benefit and scientific discovery, and collaborate with others on critical challenges, ensuring safety and ethics are the highest priority.

About you:

We seek out individuals who thrive in ambiguity and who are willing to help out with whatever moves silicon design and architecture forward. We regularly need to invent novel solutions to problems, and often change course if our ideas don’t work out, so flexibility and adaptability to work on any project is a must.

The Role:

We are seeking a talented and highly motivated hardware engineer to join our GenAI technical infrastructure research hardware team. You will have the opportunity to partake into cutting-edge architecture exploration that will shape the future of machine learning acceleration. 

Responsibilities:

• Work in a fast and interdisciplinary team bringing together experts from Machine Learning, Hardware, Programming Languages and Systems
• High performance machine learning accelerator architecture, micro-architecture and RTL design.
• Selection and integration of in-house and third party IP.
• Exploration of various trade-offs of future architecture designs in terms of performance, power, energy, and area. 
• Participate in the system architecture definition and evaluation. 
• Collaboration with simulation and PD teams to maintain up to date cost functions for architecture evaluation.

Minimum Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
• 7+ years of experience in RTL design in Verilog/System Verilog.
• 5+ years of experience in micro-architecture definition.
• 3+ years of experience in RTL design verification.
• Experience with high performance compute IPs (e.g., GPUs, DSPs, or machine learning accelerators).
• Experience in evaluating trade-offs such as speed, performance, power, area.
• Good understanding of ASIC design flow including RTL design, verification, logic synthesis and timing analysis.
• Working knowledge of transformer-based large language models.
• Hands-on knowledge of basic hardware requirements and building blocks of ML accelerators - custom number formats, matrix multiply units, vector and elementwise computation etc. 

Preferred Qualifications:

• Working experience developing with C++ & Python.
• Physical Design background or hands on experience.
• Knowledge/understanding of high level synthesis. 
• Knowledge of high performance and low power architectures for ML acceleration.
• Knowledge of processor core SoC integration 

The US base salary range for this full-time position is between $161,000 - 245,000 + bonus + equity + benefits. Your recruiter can share more about the specific salary range for your targeted location during the hiring process.

Application deadline: 12pm PST Friday February 7th, 2025

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