- Work closely with system/design team to review and understand PHY subsystem microarchitecture, create verification plans from specifications. - Build block/subsystem level test benches with reference model, using best in class DV methodology. Architect test benches with maximum reusability in mind. - Develop and execute both directed and constrained random tests, debug failures, manage bug tracking, and work with designers to drive closure of issues found. - Create and analyze block/subsystem level coverage model, and add test cases to increase coverage. - Support PHY subsystem validation using Palladium and FPGA.