Responsibilities include especially, but are not limited to: Static timing analysis for high speed IP’s, incl. analog mixed signal interfaces. CTS setup and optimisation for high frequency, multiple clocks networks. Developing floor-plans under strong area constraints with best aligned for full chip integration. Account and optimise for low power during every implementation step. Perform full place and route flow on hierarchical design blocks and meet all design targets for timing, area and power on a challenging project timeline. Implement functional, timing, noise, EMIR, etc. ECO's. Run all types of physical design verification give feedback to hard macro owners and other involved teams and perform design reviews. - Participate in physical design methodologies meetings - Assist in our AMS flow development to improve our best in class env. even further.