Signal and Power Integrity Engineer, Machine Learning

Minimum qualifications:

• PhD degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• Experience with Signal and Power Integrity (SI/PI) fundamental concepts, microwave theory, or analog circuit design.

Preferred qualifications:

• Experience in AMS (Analog Mixed Signal) design.
• Experience in Matlab, Python, C++ to establish automation flows and data processing.
• Experience with Signal and Power Integrity (SI/PI) analysis and design for high-speed digital systems, including chip-package co-design concepts.
• Experience with SIPI or microwave modeling tool chains (e.g., HFSS, ADS, Sigrity, Siwave, etc).
• Excellent programming and data analysis skills.

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

• Responsible for driving chip-package-system co-design by performing SI/PI analysis and optimization to involve in the product definition and optimize chip floorplan, power tree structure, net lists, etc for High Performance Computing (HPC) based on 2.5D/3D package technology.
• Collaborate with chip design team, system design teams and suppliers to drive chip package SI/PI design goal, define boundaries of chip design and explore SI/PI and Design for Manufacturing (DFM) trade-off for package design closure for production.
• Provide feedback on chip floorplan considering package/system routability and SI/PI.
• Develop methodology to enhance accuracy and productivity.
• Support workflows for post-silicon validation, qualification of high speed interface for New Product Introduction (NPI), high speed Interface IP evaluation (serdes, memory), and high power, large DI/DT power integrity.