- Work with systems team to understand the top level requirements of the digital functions and develop detailed specifications - Implement the function using Verilog RTL according to specification - Partition the function between HW and FW for most efficient implementation - Develop RTL and FW to implement the function - Perform unit level testing on the RTL function Other responsibilities could include: - RTL synthesis - Equivalence checking Static Timing Analysis - Develop FW to support DV and ATE environments - Support the DV team by writing self-checking tests as required
Minimum Qualifications
Minimum Qualifications
Experience in digital design including RTL design experience
Knowledge of best practices with respect to implementation of digital logic
Basic understanding of analog and full custom circuit design
Understanding of digital design flow including RTL simulation, logic synthesis, timing constraints, timing closure, STA, back annotation of parasitics, gate level simulation, equivalence checking
Basic understanding of Design Verification (DV) and the ability to write self-checking test suites
Ability to analyze a design and partition between HW implementation and SW control
Understanding of ASIC test methodology such as scan insertion, memory BIST and test pattern generation
Proficiency in English language is required
Key Qualifications
Key Qualifications
Preferred Qualifications
Preferred Qualifications
Bachelor´s degree or Master´s degree or PhD in Electrical/Computer Engineering or proven industrial experience/degree equivalent
Ability to write assembly level code and higher level code
Experience in hands-on lab evaluation
Team player with excellent written and verbal communication skills who has the desire to seek diverse challenges with international teams
Ability to work well with international teams, take ownership and motivate self and others
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