Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
  
• 3 years of experience with physical design methodology and flow validation/development methodology.
  
• Experience in floor planning and physical design tool automation with Place and Route (PnR) tools and scripting in Tcl/Perl/Shell/Python.

Preferred qualifications:

• Master's degree in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  
• Knowledge of Verilog/SystemVerilog.
  
• Understanding of circuit design, device physics and deep submicron technology.
  
• Understanding of algorithms and data structures.
  

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You will contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

• Own and Deliver synthesis to Graphic Data Stream (GDS) implementation of complex physical partitions/subsystems.
• Collaborate with cross functional teams to improve Power Performance Areas (PPAS) in physical design.
• Manage block level physical implementation and Quality of Results (QoR) on critical sensor IPs.