Staff Coherent Memory System Architect, Silicon

Minimum qualifications:

• Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.
  
• 8 years of experience in microarchitecture and design of ASIC blocks.
• Experience in micro-architecture performance analysis, tools, and simulators.
• Experience in designing or implementing RTL for one or more blocks: CPUSs, GPUs, caches, MMUs or coherent fabrics.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering or a related field.
  
• Experience in building build time configurable designs.
• Knowledge of HDL languages such as System Verilog, Verilog.
• Knowledge in one or more of these areas, Coherent interconnects, Caches, memory systems.

In this role, you will shape the future of our coherent memory systems for consumer SoCs. You will leverage your expertise in design and microarchitecture to create the most advanced, power-efficient, and performance-optimized mobile coherent systems. You will have a direct impact on the performance, efficiency, and innovation of our next-generation devices. You will collaborate with hardware designers and validation teams to build and test hardware architectures. As part of this work, you will contribute to the development of exceptional technology in the memory system and file associated patents.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

• Explore and evaluate different microarchitecture and design choices for power and performance efficient coherent memory systems.
• Author hardware microarchitecture specification for next-generation coherent memory systems.
• Analyze performance and power trade-offs.
• Work with Hardware design, verification, emulation and validation teams to build and test the hardware architecture.