Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
- 8 years of subsystem design experience.
- Experience with ASIC design methodologies for front quality checks including Lint, CDC/RDC, Synthesis, DFT ATPG/Memory BIST, UPF and Low Power Optimization/Estimation.
- Experience with RTL coding using Verilog or System verilog language.
Preferred qualifications:
- 15 years of RTL design and subsystem design experience.
- Domain knowledge in one or more of these areas: Process Cores, Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains and Pin-muxing.
- Proficient with chip design flow and good understanding of cross-domain involving DV/DFT/Physical Design/Software.
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
- Define the microarchitecture of complex IPs and subsystems and work with the team to deliver a quality, schedule compliant, and PPA optimized design.
- Work closely with the cross-functional team of Verification, Design for Test, Physical Design, and Software teams to make design decisions and represent project status throughout the development process.
- Perform RTL coding for SS/SOC integration, function/performance simulation debug, Lint/CDC/FV/UPF checks.
- Work with key design collaterals such as SDC and UPF. Work with stakeholders to discuss the right collateral quality and identify solutions/workarounds.
