FPGA Engineer at DV Trading

Job Description

About Us:

Founded more than 15 years ago and headquartered in Chicago, the DV Group of financial services firms has grown to more than 350 people operating throughout North America and in Europe. Since spinning out of a large brokerage firm in 2016, DV Trading has rapidly scaled as an independent proprietary trading firm utilizing its own capital, trading strategies, and risk management methodologies to provide liquidity to worldwide financial markets and hedging opportunities to commodity producers and users. Now, DV group affiliates include two broker dealers, a cryptocurrency market making firm, and a bourgeoning investment adviser.

We invest in exceptional individuals and empower them to realize their goals and make a lasting positive impact on our organization. Engaging a diverse group of talented people from different cultural, socioeconomic, and educational backgrounds helps provide us with a competitive advantage that drives our success.

Overview:

DV Trading LLC is looking to add an FPGA Engineer to one of its high frequency, low-latency futures trading desks. This engineer will sit alongside other FPGA Engineers and Traders to write, test, debug, and deploy new and existing FPGA trading strategies.

Responsibilities:

Write/test/debug new and existing FPGA trading strategies on futures exchanges
Manage deployments of existing algos to prod environments including compilations and updates and handling crashes/problems
Create test frameworks and unit tests for existing and new algos, including integration with software to ensure the algo passes a suite of relevant tests
Analyze performance in detail and continuously identify bottlenecks 
Interface with traders to ensure that requirements are met 
Other responsibilities as assigned by management

Requirements:

At least 3 years of professional experience developing with a commercially used HDL
(System Verilog and/or Verilog)
Completed at least one full FPGA development, design and verification cycle
Experience with FPGA development using Xilinx Vivado design software preferred
Experience using VCS, ModelSim, Questa Core or an equivalent simulation tool     
Experience with timing closure techniques for large designs
In-depth knowledge of TCP/IP protocol stack in a 10G Ethernet environment
Experience writing test benches
Experience implementing trading strategies
Experience with C/C++ and/or scripting languages such as Python

DV is not accepting unsolicited resumes from search firms. Only search firms with valid, written agreements with DV should submit resumes in response to DV’s posted positions. All resumes submitted by search firms to DV via e-mail, the Internet, personal delivery, facsimile, or any other method without a valid written agreement shall be deemed the sole property of DV, and no fee will be paid in the event the candidate is hired by DV. DV is proud to be an equal opportunity employer and committed to creating an inclusive environment for all employees.